Acorn Arcade forums: Programming: Does this form of documentation annoy you as much as me?
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Does this form of documentation annoy you as much as me? |
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Stoppers (17:51 29/10/2018)
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Simon Willcocks |
Message #124363, posted by Stoppers at 17:51, 29/10/2018 |
Member
Posts: 302
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From the ARM ARM for ARMv8: ARM DDI 0487B.a
MIOCNCE, bit [38]
Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1&0 translation
regime.
0 For the Non-secure EL1&0 translation regime, for permitted accesses to a memory
location that use a common definition of the Shareability and Cacheability of the
location, there must be no loss of coherency if the Inner Cacheability attribute for those
accesses differs from the Outer Cacheability attribute.
1 For the Non-secure EL1&0 translation regime, for permitted accesses to a memory
location that use a common definition of the Shareability and Cacheability of the
location, there might be a loss of coherency if the Inner Cacheability attribute for those
accesses differs from the Outer Cacheability attribute.
Couldn't they write:
MIOCNCE, bit [38]
Mismatched Inner/Outer Cacheable Non-Coherency Enable, for the Non-secure EL1&0 translation
regime.
For the Non-secure EL1&0 translation regime, for permitted accesses to a memory
location that use a common definition of the Shareability and Cacheability of the
location, if the Inner Cacheability attribute for those accesses differs from the
Outer Cacheability attribute:
0 there must be no loss of coherency
1 there might be a loss of coherency |
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Acorn Arcade forums: Programming: Does this form of documentation annoy you as much as me? |
