Acorn Arcade forums: Programming: How many Nops?
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How many Nops? |
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Loris |
Message #5019, posted at 15:47, 29/4/2002 |
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Heres a whimsical little challange for you. How many NOPs (no operation instructions) do you think there are in the 'standard' ARM instruction set? Example: MOV R0,R0There are obviously many more instructions, besides this 'standard' code, which do not affect any of the registers (except the usual R15 progression) or write to memory. I'd like people to publically state how many they think there are before seeing who spotted what, so no posting lists of other NOPs just yet please. PLACE YOUR BETS NOW! |
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mfrissen |
Message #5022, posted at 19:05, 29/4/2002, in reply to message #5021 |
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somewhere around 67.11M nops.. I *think* |
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monkeyson |
Message #5023, posted at 19:25, 29/4/2002, in reply to message #5022 |
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Five. |
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monkeyson |
Message #5025, posted at 11:15, 30/4/2002, in reply to message #5024 |
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Let's start a playpen thread listing them all... |
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monkeyson |
Message #5028, posted at 14:46, 30/4/2002, in reply to message #5019 |
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I'd like people to publically state how many they think there are before seeing who spotted what, so no posting lists of other NOPs just yet please. Doh, sorry, I didn't see that bit there. |
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Phlamethrower |
Message #5029, posted at 15:34, 30/4/2002, in reply to message #5028 |
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OK, using the revised rules... at least 1125. |
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monkeyson |
Message #5032, posted at 18:02, 30/4/2002, in reply to message #5031 |
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I'm hedging my bets and going for zero, on the hope that you're all disqualified due to technicalities. |
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Phlamethrower |
Message #5040, posted at 18:09, 1/5/2002, in reply to message #5039 |
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Erm, jam tomorrow. Today is 1st May. "Tomorrow" is 2nd May, please wait until I've posted my guess then post your list, I'll post mine and we can compare notes and bicker amongst ourselves. OK Maybe it isn't. I just find their contrary nature amusing. Yes. *looks up number for psychiatrist* |
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Loris |
Message #5046, posted at 13:58, 15/6/2002, in reply to message #5045 |
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did I win? Maybe, if you can give 13,694 No-ops. Here are mine, from file: op=15 opcodes x=r0-14 n=r0-15
;ineffectual movs MOVop x,x 15*15 ;operations using zero ADDop x,x,#0 5*15*15 SUB EOR BIC ORR ADDop x,x,n,LSR#32 5*15*15*16 SUB EOR BIC ORR ;avoiding carry, with carry, using zero ADCcc x,x,#0 2*15 SBCcs x,x,#0 ADCcc x,x,n,LSR#32 2*15*16 SBCcs ;bitwise operations with no effect ANDop x,x,x 2*15*15 ORR ;non-multiple load/store dr=IA,IB,DA,DB LDMopdr n[!],{} 2*15*4*15*2 STM ;branch to next instruction Bop jump 15 .jump SUBop PC,PC,#4 15 ;OK since only PC section written total 23,940 no-ops I might have given a slightly different value before; I got the digits mixed up I think. **Other not-quite generic no-ops. if we assume a 26 bit PC ARM then writes to top 6 bits are ignored if the S bit is clear therefore we can also have: SUBop PC,PC,#&v0000004 15*15 where v=1-15
and can also use the conditional PL (N flag=clear) with PC,ASR#31/32 as N flag is top bit of PC ADDpl x,x,R15,ASR#31or32 5*15*2 SUB EOR BIC ORR for an additional 375 no-ops overall total 24315 no-ops My big win was the STM x,{} instructions. I've tested them. The assembler complains about missing registers, but if supplied as a data word it works fine. doesn't seem to change the base register even if you use writeback. Doesn't matter if base points outside memory (I used negative numbers to test). And even using the program counter as base is OK.
Wha'd'ya think?
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Phlamethrower |
Message #5047, posted at 13:58, 15/6/2002, in reply to message #5046 |
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About them SWP's... I think you are right in that they won't work. I got a bit confused with the syntax |
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Mark Quint |
Message #5045, posted by ToiletDuck at 13:58, 15/6/2002, in reply to message #5044 |
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did I win? |
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Loris |
Message #5044, posted at 13:58, 15/6/2002, in reply to message #5043 |
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Fantastic. You've got a couple I didn't spot. (With apologies to anyone else with a list, I'm going to post my list later today 'cos I'm almost bursting with excitement. )
OK, my list (With a couple of extras I've just thought up), goes something like this: Original 1800: MOVop x,x ; 15*15 ADDop x,x,#0 ; 15*15 ** SUBop x,x,#0 ; 15*15 ** ANDop x,x,x ; 15*15 ORRop x,x,x ; 15*15 BICop x,x,#0 ; 15*15 ** ORRop x,x,#0 ; 15*15 ** EORop x,x,#0 ; 15*15 **New ones: CMPEQ n,n ; 15 (Not quite under all conditions I think)
This hadn't occurred to me. What conditions doesn't it work under? Presumably it will modify carry - anything else? How about the compare which doesn't affect carry? TEQEQ n,n ; 15 sweeet. ADCCC x,x,#0 ; 15 ** SBCCC x,x,#0 ; 15 **
These were some of the ones I found amusing. I'm not sure, but I think the bottom one should be: sbcCS x,x,#0 because it uses NOT(carry).
Bleh. Can't be bothered thinking up any more. That's 1845 for that lot.The ones marked **: Although no compiler is likely to produce them, I think it may be possible to make use of the shift amount used when representing constants (i.e. &8000 is stored as &02 with a shift of 9 (Each shift corresponds to two bits)). This would make 16 times as many no-ops for those, boosting my total to 19170. I think these are excluded under the 'minimum barrel shift' requirement that Acorn made. However I think they do work, at least on current ARMs. I'm willing to be persuaded if anyone knows different. One similar thing I used was to use a register LSR#32. This is accepted by the compiler and swells the ranks considerably. Unfortunately LSL#32 and ROR#32 are not allowed. I also found some other interesting shifted ops which I don't think are quite permissable, I'll post these up later.There is also my SWP instruction(s):SWPop[B] x,x,[y] ; 15*2*15*15 SWPop[B] x,x,[y,#blarg] ; 15*2*15*15*256*16 ... etc for all other [reg,offset] stuff However since y may not be a valid place in memory, I'm not counting these instructions (And I can't be bothered to work out how many there are ) Hmmm, won't these store x at [y] and set the register to y? Interesting, though. I'd have thought the byte operations would excise the top 3 bytes of the register at least. If they do what you imply, could you get round the memory position requirement by using PC, ie to use the position of the instruction itself? |
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Phlamethrower |
Message #5020, posted at 13:58, 15/6/2002, in reply to message #5019 |
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Can't you do something useful instead? Um, OK then, over 24 million. Seriously. |
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Phlamethrower |
Message #5043, posted at 13:58, 15/6/2002, in reply to message #5042 |
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OK, my list (With a couple of extras I've just thought up), goes something like this: Original 1800: MOVop x,x ; 15*15 ADDop x,x,#0 ; 15*15 ** SUBop x,x,#0 ; 15*15 ** ANDop x,x,x ; 15*15 ORRop x,x,x ; 15*15 BICop x,x,#0 ; 15*15 ** ORRop x,x,#0 ; 15*15 ** EORop x,x,#0 ; 15*15 **New ones: CMPEQ n,n ; 15 (Not quite under all conditions I think) ADCCC x,x,#0 ; 15 ** SBCCC x,x,#0 ; 15 **
Bleh. Can't be bothered thinking up any more. That's 1845 for that lot. The ones marked **: Although no compiler is likely to produce them, I think it may be possible to make use of the shift amount used when representing constants (i.e. &8000 is stored as &02 with a shift of 9 (Each shift corresponds to two bits)). This would make 16 times as many no-ops for those, boosting my total to 19170. There is also my SWP instruction(s): SWPop[B] x,x,[y] ; 15*2*15*15 SWPop[B] x,x,[y,#blarg] ; 15*2*15*15*256*16 ... etc for all other [reg,offset] stuff However since y may not be a valid place in memory, I'm not counting these instructions (And I can't be bothered to work out how many there are ) |
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Loris |
Message #5042, posted at 13:58, 15/6/2002, in reply to message #5041 |
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FTP co-processor Heh, now that's a good one, made me smile I think you meant FP co-processor, although I'd just assume it's not present, then all its instructions are faults
Uh, mnk nk grmp. </Henry Crun>Yeh. OK. I reckon I've got 23,490 no-ops. Some may be disqualified, but I hope not Also I might have added up wrong, YMMV. I kind of hope theres still a few more out there.. So, what are the entries? Mr Jake Monkeyson ( ) 5 (or zero as backstop) Jeffry Lee ( ) 1,125 or 1,800 Mark Quint ( ) 13,694 Tony Haines ( ) 23,490 So, does anyone want to post a breakdown? I don't have my complete description with me today; its on my 'puter. I suggest the following notation: Use standard ARM assembly format, with the following indicating a degeneracy - op = any opcode other than NV x,y,z stand for any register except R15 n,m,o = any register [optional] other additions as necessary where more than one instruction has the same format, only write out the first one in full, then just the differing part examples which I expect we've all got: MOVop x,x 15*15 instructions
ADDop x,x,#0 2*15*15 SUB Come on then - lets have it. Oh, and please describe any which nearly work but not under all conditions. |
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john |
Message #5041, posted at 13:58, 15/6/2002, in reply to message #5030 |
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FTP co-processor
Heh, now that's a good one, made me smile I think you meant FP co-processor, although I'd just assume it's not present, then all its instructions are faults |
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Loris |
Message #5039, posted at 13:58, 15/6/2002, in reply to message #5037 |
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I'd say that the instruction should always do nothing under any circumstances. I had an idea for a couple I really liked, but unfortunately they might mung things sometimes so no good. OK
Well... sometimes an instruction will generate an error, but that is OK, provided it isn't the instructions 'fault'. For example, if it were in the last accessable position in memory, you'd get an address exception 'cos it couldn't read the next instruction. But that is OK because a normal instruction would too. <snip>
Is that today-tomorrow or tomorrow-tomorrow? Erm, jam tomorrow. Today is 1st May. "Tomorrow" is 2nd May, please wait until I've posted my guess then post your list, I'll post mine and we can compare notes and bicker amongst ourselves.I've got no idea how you can have a hilarious instruction. Maybe it isn't. I just find their contrary nature amusing. |
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monkeyson |
Message #5038, posted at 13:58, 15/6/2002, in reply to message #5037 |
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Is that today-tomorrow or tomorrow-tomorrow?
Or even MicroDigital tomorrow???
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Phlamethrower |
Message #5037, posted at 13:58, 15/6/2002, in reply to message #5036 |
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I'd say that the instruction should always do nothing under any circumstances. I had an idea for a couple I really liked, but unfortunately they might mung things sometimes so no good. OK One thing I should point out is that the only restriction on the number of cycles taken is that it should be finite. Um, er, OK I think. Please wait till tomorrow at least before giving your list - I've not done the testing I need to do yet. (I've got a couple of hilarious instructions that I need to check). Is that today-tomorrow or tomorrow-tomorrow? I've got no idea how you can have a hilarious instruction. Don't know how many i'll have, but I think quite a lot. Good |
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Loris |
Message #5036, posted at 13:58, 15/6/2002, in reply to message #5034 |
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Now upgraded to 1800, plus several hundred more if you include SWP (Very dodgy use though that won't work all the time).All checked against the PRM, and isn't likely to get much higher than that number I'd say that the instruction should always do nothing under any circumstances. I had an idea for a couple I really liked, but unfortunately they might mung things sometimes so no good. One thing I should point out is that the only restriction on the number of cycles taken is that it should be finite. Please wait till tomorrow at least before giving your list - I've not done the testing I need to do yet. (I've got a couple of hilarious instructions that I need to check). Don't know how many i'll have, but I think quite a lot. |
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Phlamethrower |
Message #5035, posted at 13:58, 15/6/2002, in reply to message #5034 |
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Come on, before I get bored and post how I got them |
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Phlamethrower |
Message #5034, posted at 13:58, 15/6/2002, in reply to message #5033 |
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Now upgraded to 1800, plus several hundred more if you include SWP (Very dodgy use though that won't work all the time). All checked against the PRM, and isn't likely to get much higher than that number |
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Phlamethrower |
Message #5033, posted at 13:58, 15/6/2002, in reply to message #5030 |
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OK, using the revised rules... at least 1125. Hmmm. I don't see this as a revision - obviously standard means different things to different people. So some clarification is in order.
I can list every single one of them (Given several minutes to write a program to generate the list ) Excluded series of instructions: FTP co-processor Thumb DSP, jazelle or any other of those funny recent additional instructions Any instructions Acorn or ARM have indicated as undefined operation, which may currently work as NOPs but may change in future ARMs. For example this group includes ~NV instructions, or those using #0 but shifted in any way. (Acorn stated that for absolute values the lowest barrel shift possible must be used) erm any others?
None of them. |
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Mark Quint |
Message #5031, posted by ToiletDuck at 13:58, 15/6/2002, in reply to message #5030 |
Quack Quack
Posts: 1016
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i havent posted yet! I dont have time to estimate it, *but*! from a quick estimate using 2ish years of geographical expertise in "estimating" numbers, i'd say around 13,694. |
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Loris |
Message #5030, posted at 13:58, 15/6/2002, in reply to message #5029 |
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OK, using the revised rules... at least 1125. Hmmm. I don't see this as a revision - obviously standard means different things to different people. So some clarification is in order. Excluded series of instructions: FTP co-processor Thumb DSP, jazelle or any other of those funny recent additional instructions Any instructions Acorn or ARM have indicated as undefined operation, which may currently work as NOPs but may change in future ARMs. For example this group includes ~NV instructions, or those using #0 but shifted in any way. (Acorn stated that for absolute values the lowest barrel shift possible must be used) erm any others? Sorry if this message is a little garbled, I'm not entirely sober - my tolerance for alcohol seems very low ATM. Monkeyson- 's OK, no harm done. |
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Loris |
Message #5027, posted at 13:58, 15/6/2002, in reply to message #5026 |
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Mr Lee knows this already, but I'm posting this here in case anyone here doesn't go in the playpen (yeah right ) I said:
NV instructions don't count as they are depreciated. IIRC their execution became undefined when someone at Acorn or ARM worked out they could be used for other things and everyone could use MOV R0,R0 (or something else) as no-op anyway. This only makes it all the more exciting really, because all the others are therefore so much more important. |
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Phlamethrower |
Message #5026, posted at 13:58, 15/6/2002, in reply to message #5024 |
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Um, have you counted? No, but I know that there should be at least 24 million of them. If I was to explain how then I'd give it all away I am going to check your working.. (I'll have to make my own calculation first..) A look through the PRMs is all that's needed. |
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Loris |
Message #5024, posted at 13:58, 15/6/2002, in reply to message #5020 |
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Can't you do something useful instead? Um, OK then, over 24 million. Seriously. Um, have you counted? I am going to check your working.. (I'll have to make my own calculation first..) |
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Phlamethrower |
Message #5021, posted at 13:58, 15/6/2002, in reply to message #5020 |
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Actually, somewhere between 24 million and 268435456. Probably about 134217728. Max. Bleh! Why am I wasting my time on this when I know I'll be the only one to reply? |
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Jeffrey Lee |
Message #73657, posted by Phlamethrower at 01:42, 21/1/2006, in reply to message #5047 |
Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot stuff
Posts: 15100
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How about:
y=x,s z=f,c MSRcc CPSR_y, n ; 15*2*15 MSRcc CPSR_y, #n ; 15*2*(128*16+1) (I think that's the right formula for a minimum shift wotsit) MSRcc CPSR_z, #n ; 15*2*(128*12+0.5) (Since 0 will only work with one of them)
OK, the first two are a bit dodgy, depending on whether those bits of the PSR are used yet. And also whether your CPU supports the instruction, since I can't seem to find a mention of the CPSR_c, CPSR_x, or CPSR_s versions of the instruction in the ARM7 datasheet. The third one should be fine though, as it tries to write a value to an area of the PSR that is masked off (Although if the CPSR_c form doesn't exist, that variant won't work either ). And if CPSR_x and/or CPSR_s exist and cause bad stuff to happen when you write to them, you can also write to the bits that aren't written to instead.
So in summary: * If only CPSR_f exists, +15*(128*12+1)=23,055 points for me * If CPSR_c exists also, it's an extra 23,040 no-ops * If CPSR_x and CPSR_s exist but cause bad stuff to happen, add another 46,110 no-ops onto that * But if they exist and aren't used for stuff, add 15*2*(128*4+14)=15,780 onto that
So assuming a best-case scenario, I now have about 109,830 no-ops. SO THERE.
And if you're in user mode, the number will increase even further, as all CPSR_x/CPSR_s/CPSR_f instructions will be ignored
[Edited by Phlamethrower at 01:49, 21/1/2006] |
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Acorn Arcade forums: Programming: How many Nops? |
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