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ARM Assembler Optimization |
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finkel (11:08 26/11/2010)
nunfetishist (15:06 26/11/2010)
monkeyson2 (22:38 26/11/2010)
hubersn (22:50 26/11/2010)
trevj (22:50 26/11/2010)
Phlamethrower (22:57 26/11/2010)
monkeyson2 (01:03 27/11/2010)
VincceH (12:16 27/11/2010)
trevj (10:32 28/11/2010)
qUE (02:09 30/11/2010)
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John Smith |
Message #115923, posted by finkel at 11:08, 26/11/2010 |
Member
Posts: 1
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Hi everyone,
I need some documentation on how to optimize assembler code for pipeline execution on ARM11 processor.
I remember some general rules for some generic RISC CPU from my university days, like branch prediction, instruction interleaving, computational dependencies, etc, but I have only some vague ideas what I should be doing with ARM11.
I downloaded some technical references from the net, so at least I know that ARM11 has 8 pipeline stages, early-stage branch prediction, and so on, but some specific answers are hard to find.
For example, if I write something like this...
tst r0,#1
<other instructions>
beq l1
... how many other (non-dependent) instructions should I put between tst and beq so that pipeline doesn't stall, and flushes minimal number of instructions in case of branch misprediction?
Similar question for something like this:
add r0,#1
<other instructions>
add r1,r0 ;@ write-read dependence of r1 on r0
Has anyone seen any online documentation dealing with this kind of stuff? |
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Rob Kendrick |
Message #115924, posted by nunfetishist at 15:06, 26/11/2010, in reply to message #115923 |
 Today's phish is trout a la creme.
Posts: 524
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Has anyone seen any online documentation dealing with this kind of stuff? Yes. The ARM ARM. (ARM Architectural Reference Manual.) It contains most, if not all, of the information you are after. |
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Phil Mellor |
Message #115927, posted by monkeyson2 at 22:38, 26/11/2010, in reply to message #115924 |
 Please don't let them make me be a monkey butler
Posts: 12380
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Has anyone seen any online documentation dealing with this kind of stuff? Yes. The ARM ARM. (ARM Architectural Reference Manual.) It contains most, if not all, of the information you are after.
The Advanced Reduced Instruction Set Computer Machine Reference Manual?! |
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Steffen Huber |
Message #115928, posted by hubersn at 22:50, 26/11/2010, in reply to message #115927 |
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Posts: 91
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Has anyone seen any online documentation dealing with this kind of stuff? Yes. The ARM ARM. (ARM Architectural Reference Manual.) It contains most, if not all, of the information you are after.
The Advanced Reduced Instruction Set Computer Machine Reference Manual?!
My personal favourite of the category "abbreviation cluster" is ITOC.
ITOC = IMS TCP/IP OTMA Connection |
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Trevor Johnson |
Message #115929, posted by trevj at 22:50, 26/11/2010, in reply to message #115927 |
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Posts: 660
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The Advanced Reduced Instruction Set Computer Machine Reference Manual?! <pedant> Advanced Reduced Instruction Set Computer Machines Architectural Reference Manual</pedant>
[Edited by trevj at 22:51, 26/11/2010] |
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Jeffrey Lee |
Message #115930, posted by Phlamethrower at 22:57, 26/11/2010, in reply to message #115929 |
 Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot Hot stuff
Posts: 15100
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Except it's the Architecture reference manual  |
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Phil Mellor |
Message #115931, posted by monkeyson2 at 01:03, 27/11/2010, in reply to message #115930 |
Please don't let them make me be a monkey butler
Posts: 12380
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After all this I can see why they abbreviated it to ARM ARM.  |
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VinceH |
Message #115932, posted by VincceH at 12:16, 27/11/2010, in reply to message #115931 |
 Lowering the tone since the dawn of time
Posts: 1600
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After all this I can see why they abbreviated it to ARM ARM. Yes, because "Computer Machines" sounds so "I don't have much truck with those computer machines, they're almost as bad as that book learning." |
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Trevor Johnson |
Message #115933, posted by trevj at 10:32, 28/11/2010, in reply to message #115930 |
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Posts: 660
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Except it's the Architecture reference manual That's actually what I put before I did the edit! |
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qUE |
Message #115958, posted by qUE at 02:09, 30/11/2010, in reply to message #115923 |
Posts: 187
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ARM website has pretty much all the info you need, you'll just have to hunt for it.
The newer ARM chips are very different from the older ones like I'm used to. I'm not sure optimisations like using conditioned instructions rather than branches have quite the same impact they had on ye olde chips. Simple optimisations like bitshift to multiply/divide will still work though. And obviously using the registers as much as possible to avoid accessing memory will have a massive impact on performance. RAM access is slow on any machine...well...until the RAM speed matches the CPU speed, which isn't far off being the norm. |
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