Acorn Arcade forums: Programming: Mov al,es:[bx] ???Help me please
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Mov al,es:[bx] ???Help me please |
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Blacknight (09:40 20/5/2003)
not_ginger_matt (10:22 2/6/2003)
Loris (13:54 2/6/2003)
not_ginger_matt (14:24 2/6/2003)
Loris (17:03 2/6/2003)
rich (09:06 3/6/2003)
Loris (10:08 3/6/2003)
johnstlr (14:52 2/6/2003)
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Matan Argaman |
Message #42515, posted by Blacknight at 09:40, 20/5/2003 |
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Posts: 1
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Mov al,es:[bx]
I wrote the following to get the color of the point i pressed on with the mouse(in asm ofcourse). Bx, holds the current position of the point. for some reason this only works if I use the step by step run time(pressing f7 and then f8 to move to the next command), and then only if i put a break point before this line, if i put a break point right after it, it always returns a zero. Damn it!!!help!!! |
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Richard Wilson |
Message #43118, posted by not_ginger_matt at 10:22, 2/6/2003, in reply to message #42515 |
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Posts: 63
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Mov al,es:[bx]
I wrote the following to get the color of the point i pressed on with the mouse(in asm ofcourse). Bx, holds the current position of the point. for some reason this only works if I use the step by step run time(pressing f7 and then f8 to move to the next command), and then only if i put a break point before this line, if i put a break point right after it, it always returns a zero. Damn it!!!help!!! I'm not sure what assembler you're using as the syntax is not one I'm familiar with, but what you want to be doing something like...
// r0 = screen base
// r1 = width of screen in bytes
// r2 = X position
// r3 = Y position
MLA r4,r2,r1,r3
LDRB r4,[r0,r4]
// r4 is now the value of (r2,r3)
...for an 8-bit screen, changing the LDRB to a LDRH for 16-bit and to a LDR for 32-bit. Of course LDRH isn't supported on most RISC OS hardware so you'll need to do...
MLA r4,r2,r1,r3
LDRB r4,[r0,r4]!
LDRB r5,[r0,#1]
ORR r4,r4,r5,lsl #8
...which will corrupt r0 and r5, be slower, but work everywhere. |
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Tony Haines |
Message #43131, posted by Loris at 13:54, 2/6/2003, in reply to message #43118 |
 Ha ha, me mine, mwahahahaha
Posts: 1025
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...for an 8-bit screen, changing the LDRB to a LDRH for 16-bit and to a LDR for 32-bit. Of course LDRH isn't supported on most RISC OS hardware so you'll need to do... LDRH works on StrongARM...
But maybe not for screen memory I dunno. (I think it might work if the data gets cached only.)
MLA r4,r2,r1,r3
LDRB r4,[r0,r4]!
LDRB r5,[r0,#1]
ORR r4,r4,r5,lsl #8
...which will corrupt r0 and r5, be slower, but work everywhere. It might be better to do
...
LDR r4,[r0,r4]
MOV R4,R4,LSL#16
MOV R4,R4,LSR#16
which corrupts less registers, less memory accesses and uses the same number of instructions. Or less if you can incorporate those shifts into other instructions.
I'd try to get another useful instruction after the ldr if possible. This will be done 'for free' on some architectures (StrongARM and above). |
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Richard Wilson |
Message #43153, posted by not_ginger_matt at 14:24, 2/6/2003, in reply to message #43131 |
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Posts: 63
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...for an 8-bit screen, changing the LDRB to a LDRH for 16-bit and to a LDR for 32-bit. Of course LDRH isn't supported on most RISC OS hardware so you'll need to do... LDRH works on StrongARM...
But maybe not for screen memory I dunno. (I think it might work if the data gets cached only.)
It will only work from data which is cached. From memory, it's the RPC's bus that doesn't support LDRH - something that was rectified by Phoebe, and I presume Iyonix/Omega (not had chance to test this out yet).
MLA r4,r2,r1,r3
LDRB r4,[r0,r4]!
LDRB r5,[r0,#1]
ORR r4,r4,r5,lsl #8
...which will corrupt r0 and r5, be slower, but work everywhere. It might be better to do
...
LDR r4,[r0,r4]
MOV R4,R4,LSL#16
MOV R4,R4,LSR#16
which corrupts less registers, less memory accesses and uses the same number of instructions. Or less if you can incorporate those shifts into other instructions.
I'd try to get another useful instruction after the ldr if possible. This will be done 'for free' on some architectures (StrongARM and above).
I was going to put this, but I couldn't remember if the rotation of words was guaranteed for all revisions of ARM processors :-(. I certainly seem to recall some discussion about LDM not always masking out the bottom 2 bits of the address, but I can't remember the specifics at the moment (although every chip currently used on RISC OS hardware will exhibit the expected LDR/LDM behaviour).
Anyway, if we're talking about optimisation and you are not bothered about the top 16-bits being 'garbage' then no masking is required at all. Alternatively, if you're doing a lot of reading, and need purely the half-word, you can set up a mask to do it in a single instruction each time...
MVN r12,#0
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LDR r4,[r0,r4]
AND r4,r4,r12,LSL #16
...which with some simple re-arrangement will make even the single case faster as you can eat up the stall cycle by setting up the mask after the load.
I'm not quite sure why, but this all reminds me of one of my favourite ARM code sequences for working with 16-bit numbers...
MOV r1,r0,LSR #16
BIC r0,r0,r1,LSL #16
...which puts the high half-word of r0 into r1 and the low one into r0, both masked off. Then there's the swapping of two registers without an intermediate by EORing them together a few times which is lovely when working with very tight code (EOR r0,r0,r1:EOR r1,r0,r1:EOR r0,r0,r1).
I'm sure this has been asked a million times before, but is there a site anywhere with snippits of cute ARM code chunks?
[Edited by not_ginger_matt at 15:24, 2/6/2003] |
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Lee Johnston |
Message #43157, posted by johnstlr at 14:52, 2/6/2003, in reply to message #43118 |
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Posts: 193
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I'm not sure what assembler you're using as the syntax is not one I'm familiar with,
*snip*
It looks like x86 to me so you have to wonder why it was posted here. |
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Tony Haines |
Message #43170, posted by Loris at 17:03, 2/6/2003, in reply to message #43153 |
Ha ha, me mine, mwahahahaha
Posts: 1025
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I'm not quite sure why, but this all reminds me of one of my favourite ARM code sequences for working with 16-bit numbers...
MOV r1,r0,LSR #16
BIC r0,r0,r1,LSL #16
...which puts the high half-word of r0 into r1 and the low one into r0, both masked off. Then there's the swapping of two registers without an intermediate by EORing them together a few times which is lovely when working with very tight code (EOR r0,r0,r1:EOR r1,r0,r1:EOR r0,r0,r1).
I'm sure this has been asked a million times before, but is there a site anywhere with snippits of cute ARM code chunks? Steven Singer's site is a good one.
Alain Brobecker's site seems to have recently moved here. You'll probably want the ASM Tricks article.
I have a few routines posted I've found around the place over the years which possibly don't exist on the net any more. Stuff like finding the first or last bit set in a word, reversing a word, that sort of thing..
A guy called Wilco used to have amazing solutions to this sort of thing, IIRC.
Maybe the Kon Bar could host a large compilation of all these little things? |
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Richard Goodwin |
Message #43174, posted by rich at 09:06, 3/6/2003, in reply to message #43170 |
 Dictator for life
Posts: 6828
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Yup, write it up and send it in!
________
 Cheers,
Rich.
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Tony Haines |
Message #43179, posted by Loris at 10:08, 3/6/2003, in reply to message #43174 |
Ha ha, me mine, mwahahahaha
Posts: 1025
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OK, I'll accept contributions, although I don't promise to use them.  |
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Acorn Arcade forums: Programming: Mov al,es:[bx] ???Help me please |
