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Memory map |
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andrew (14:03 18/6/2004)
ninj (15:57 18/6/2004)
Loris (15:59 18/6/2004)
john (16:18 18/6/2004)
andrew (20:05 18/6/2004)
john (20:52 18/6/2004)
andrew (12:15 19/6/2004)
Lampi (13:40 19/6/2004)
adrianl (19:46 19/6/2004)
john (13:45 20/6/2004)
andrew (16:03 20/6/2004)
john (00:02 21/6/2004)
Lampi (15:49 21/6/2004)
andrew (22:27 21/6/2004)
adrianl (02:00 22/6/2004)
andrew (14:41 23/6/2004)
adrianl (21:36 23/6/2004)
andrew (00:03 25/6/2004)
Loris (09:12 22/6/2004)
andrew (14:41 23/6/2004)
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Andrew |
Message #55804, posted by andrew at 14:03, 18/6/2004 |
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In RISC OS 3, there is supposed to be a 'logical' and 'physical' memory map.
AIUI the logical map is there to allow programs to think they are using the same area of memory but in fact can be shuffled around by the OS. But there was only a maximum of 16MB in RISC OS computers up to 3.1 so doesn't this mean that there is a huge amount of the 26bit address but being wasted?
i.e. 32MB logical memory
16MB allotment for actual RAM
48MB of addresses for ROM?
Where does the workspace for various parts of the OS go? In the BBC it came before user RAM which in turn was before screen memory then ROM.
[Forgot to Select 'Programming' section]
[Edited by andrew at 15:05, 18/6/2004] |
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ninjah |
Message #55815, posted by ninj at 15:57, 18/6/2004, in reply to message #55804 |
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Eh, my memory of this is a bit hazy, but it's the MMU which translates from logical addresses to physical addresses. I believe that in anything but user mode, the MMU is bypasses, therefore when executing any interrupt handlers or SWIs (i.e. when running OS code) the logical address space is not used. Similarly, the workspace for the kernel and OS modules doesn't need to me mapped into the logical space. |
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Tony Haines |
Message #55817, posted by Loris at 15:59, 18/6/2004, in reply to message #55804 |
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Acorn reserved it for future expansion 
What are you actually worrying about here?
That a few bits of PC never got set to 1?[1]
If you had a lot of RAM you could use all of it, although perhaps with old-style organisation only a certain amount in a single task. Iyonixes can use it all in a single task IIRC.
There are memory maps for the old 'puters knocking about - have a look in StrongHelp manuals.
The OS does a lot of paging memory in and out as tasks are called. Tasks not in use have their memory paged out so it can't accidentally be written to. Read/writes to memory which isn't part of the logical map cause address exceptions. This is the OS's way of telling the programmer to slow down.
Also in later machines this is how dynamic areas can grow and shrink without fragmenting in the logical memory map.
[1] in normal usage - this may be different if virtual memory is involved, but don't take my word for it. |
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John D |
Message #55818, posted by john at 16:18, 18/6/2004, in reply to message #55804 |
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More like 16MB for any application that's paged in, 16MB (say, can't remember off hand) for RAM disc, 8MB for the RMA, 1MB for the system heap and SVC stack, 1MB for the font cache etc.
Basically everything you see in the task manager has some logical address space. Depending how much you drag the bars alters where the physical pages are mapped. This allows the font cache to use the same adrea of logical memory even though the pages in physical memory may have been used for something else at some other point.
I hope that makes sense! |
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Andrew |
Message #55842, posted by andrew at 20:05, 18/6/2004, in reply to message #55818 |
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I see so the logical memory is dynamic and makes use of the physical memory how it wants to without the user having to know about it. That's quite a step up from the old computers and something i didn't really think about when the ARM machines were released (or RISC OS 2, don't know if Arthur had dynamic memory).
In some ways then, the logical memory layout is very similar to the Beeb's RAM in that the bottom few bytes are system workspace and then other work areas and finally screen memory (presumably freed up for ordinary RAM on the RPC).
So how do RISC OS 3.5> computers make use of >32MB RAM? |
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John D |
Message #55847, posted by john at 20:52, 18/6/2004, in reply to message #55842 |
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All wimp tasks get mapped in at &8000 and the slot on RO3.5 is bigger (26M or so) because some stuff has been moved. You can have as many tasks as you like (assume so for this purpose) so you can have as many lots of 26MB as you like all used at once (but not mapped in).
Then of course there are dynamic areas which are above 64M in the memory map, they can go up to 4GB in the map so there's a lot of scope for lage memory. Basucally you don't have to care about amount of RAM, you just ask for ram and it either appears where you expect or you get an error. Very handy. You could even have more than 4GB of ram and as long as the OS and MMU etc could hand'e it Aaps wpuldn't care as long as they see themselfs at &8000. The iyonic can have 512MB tasks IIRC due to the module area (RMA) being moved. On RO3/4 this isn't possible because the cpu is in 26 bit mode. But that's another discussion altogether.
NB I've been to the pub so this may well not make sense, but it looks right to me ;) |
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Andrew |
Message #55855, posted by andrew at 12:15, 19/6/2004, in reply to message #55847 |
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The thing I'm trying to understand though is how with a 26bit address bus RISC OS 3.5> is able to access addresses above 64MB. I don't have the memory map for 3.5> but I'm assuming as you say that things have been moved, but how would the next 64MB be accessed? I was under the impression that it could only access 64MB at once so I'm assuming there is some kind of hardware solution. |
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James Lampard |
Message #55859, posted by Lampi at 13:40, 19/6/2004, in reply to message #55855 |
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It's a 32bit address bus on ARM6 and later, but for backward compatibility it runs with a 26bit *program counter*.
Ie programs have to be in the bottom 64MB but data can be at any addresss. (using dynamic areas above 64MB )
[Edited by Lampi at 14:40, 19/6/2004] |
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Adrian Lees |
Message #55861, posted by adrianl at 19:46, 19/6/2004, in reply to message #55859 |
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And just to complicate things further, it runs in 32-bit configuration, but a 26-bit mode so you /can/ execute above 64MB, by entering a 32-bit mode. However, prior to RO4 (I think) you had to disable IRQs first, and you couldn't call any SWIs because the OS would assume you were calling from a 26-bit mode.
An early version of Aemulor ran on RO4 but in a 32-bit mode for testing purposes, and it manually switched back from 26- to 32-bit mode after every SWI it called! 
Oh yeah, and the RiscPC has only a 29-bit physical address bus, (it converts 32-bit logical addresses into physical addresses before accessing DRAM and I/O space etc.).
Confused yet? 
[Edited by adrianl at 20:49, 19/6/2004] |
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John D |
Message #55877, posted by john at 13:45, 20/6/2004, in reply to message #55861 |
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Oh yeah, and the RiscPC has only a 29-bit physical address bus, (it converts 32-bit logical addresses into physical addresses before accessing DRAM and I/O space etc.).
'It' being the ARM's MMU that was mentioned earleir. Of course you can only have not much more than 256M in a Risc PC but you can similarly have more than the amount of logical address space jusdt by having more bits on the physical address bus :). |
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Andrew |
Message #55884, posted by andrew at 16:03, 20/6/2004, in reply to message #55877 |
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What is an MMU?
I'm not making sense of this. AIUI the address but accessed by the 26bit program counter was used to bring data to the CPU from RAM. Thus if there is RAM above 64MB how is it brought to the CPU?
[Edited by andrew at 17:06, 20/6/2004] |
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John D |
Message #55891, posted by john at 00:02, 21/6/2004, in reply to message #55884 |
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Memory management unit or similar. Basically translates the logical addresses used by the ARM into the physical addresses used by the hardware.
Assuming the MMU is enabled (which is a fair assumption) the 26 bit PC has a logical address in it. Therefore it can only execute *code* below 64MB in logical memory. This means mainly the wimp task slot and the RMA.
However, instructions such as LDR take a 32 bit register, so they can use *data* from anywhere in the logical memory map.
The mapping between pages (4K chunks usually here) of logical and physical memory may be changed at any time by RISC OS, and every time a task switch happens some other physical memory is mapped in starting at &8000. This means you can have >64MB worth of code "loaded" at the same time but of course only some of it is visible.
Anyway, that's about as well as it can be explained, you'd be far better off reading a text book to get the basics.
Hope this helps. |
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James Lampard |
Message #55920, posted by Lampi at 15:49, 21/6/2004, in reply to message #55884 |
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The 26bit program counter is used to fetch *code* only.
The other regs are 32bit, data loaded using addresses stored in these can be anywhere in the memory map. |
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Andrew |
Message #55945, posted by andrew at 22:27, 21/6/2004, in reply to message #55920 |
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So it was just really applications that have to be below 23MB in length but dynamic areas provided the memory above that. Making sense now
AL - I try to avoid thinking of the StrongARM being in fact 32bit as that is too mind-bogling. I'll cross that bridge when I get an Iyonix  |
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Adrian Lees |
Message #55949, posted by adrianl at 02:00, 22/6/2004, in reply to message #55945 |
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So it was just really applications that have to be below 23MB in length but dynamic areas provided the memory above that. Making sense now
AL - I try to avoid thinking of the StrongARM being in fact 32bit as that is too mind-bogling. I'll cross that bridge when I get an Iyonix
ARM6 through to StrongARM have both 26- and 32-bit modes, but that isn't complicated... mostly it's just a flag that says whether the PC (program counter, holds the address of the current instruction), is treated as just 26 bits or the full 32.
We were lucky that the 26-bit modes weren't dropped with the StrongARM (or perhaps unlucky, because it meant RO didn't have to move forwards). Plus, frankly, 32-bit mode is simpler to understand. (The 26-bit PC was a neat trick at the time but it became a limitation and, rightly, was dropped.)
[Edited by adrianl at 03:03, 22/6/2004] |
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Tony Haines |
Message #55953, posted by Loris at 09:12, 22/6/2004, in reply to message #55945 |
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I try to avoid thinking of the StrongARM being in fact 32bit as that is too mind-bogling. I'll cross that bridge when I get an Iyonix To be honest I'm wondering why you are worrying about it at all.
Is it:
1) You are planning on writing a massive, huge application.
2) You want to muck around with interrupts or vectors and think you should worry (although you probably don't)
3) Some other specialised application you have
4) General interest
5) other
? |
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Andrew |
Message #56067, posted by andrew at 14:41, 23/6/2004, in reply to message #55953 |
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I want to understand at a basic level whats going on and how things have evolved. I haven't really thought about it much as I've just accepted that memory is reserved somehow for tasks/BASIC/whatever.
Interrupts is something I might want to look into at some point for perhaps scrolling backgrounds for example. Saw it done on the BBC Micro. |
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Andrew |
Message #56068, posted by andrew at 14:41, 23/6/2004, in reply to message #55949 |
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So it was just really applications that have to be below 23MB in length but dynamic areas provided the memory above that. Making sense now
AL - I try to avoid thinking of the StrongARM being in fact 32bit as that is too mind-bogling. I'll cross that bridge when I get an Iyonix
ARM6 through to StrongARM have both 26- and 32-bit modes, but that isn't complicated... mostly it's just a flag that says whether the PC (program counter, holds the address of the current instruction), is treated as just 26 bits or the full 32.
We were lucky that the 26-bit modes weren't dropped with the StrongARM (or perhaps unlucky, because it meant RO didn't have to move forwards). Plus, frankly, 32-bit mode is simpler to understand. (The 26-bit PC was a neat trick at the time but it became a limitation and, rightly, was dropped.)
[Edited by
at 03:03, 22/6/2004]
We really need some new PRMs more than ever. Is there printed material with the new Castle DDE? |
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Adrian Lees |
Message #56114, posted by adrianl at 21:36, 23/6/2004, in reply to message #56068 |
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There's still a fair bit of info missing from the on-line/PDF documentation that's available 
I've had to obtain a fair bit of info for my projects by reverse-engineering. Sshh. Don't tell anyone! |
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Andrew |
Message #56214, posted by andrew at 00:03, 25/6/2004, in reply to message #56114 |
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If you're good enough to reverse engineer you don't need manuals |
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